74HC Datasheet, 74HC stage Binary Counter Datasheet, buy 74HC, 74HC pdf, ic 74HC description/ordering information. The ‘HC devices are stage asynchronous binary counters, with the outputs of all stages available externally. A high. Data sheet acquired from Harris Semiconductor. SCHSD. Features. • Fully Static Operation. • Buffered Inputs. • Common Reset. • Negative.

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I saw the 25 MHz trick in your terminal project – good to know. I have a tube of 50 MHz cans around here that I could divide down, but since I have to order parts for this thing anyway, I might as well pick up the exact frequency for a few bucks. I have to go take them out of my shopping cart now: Interestingly, it also has a synchronous clear, and connections for synchronous expansion between counters with lookahead carry outputs.

Even if you could output a new address every cycle, that’s still only about half of the Interesting discovery upon looking back All these numbers involving multiples of propagation-delays are making me question even further how I got the ol’ LCD controller running.

What about using the fastest PIC available and bitbanging the address lines? Now, I need 5 ICs to make the counter – if it’s even fast enough.

I’m going to ignore those timing calculations for the moment next log because there’s an even bigger problem here – it takes too long for the address to settle.

This could be interesting. Let’s run the numbers, using a 15pF load: I can hook one to the four-channel scope and have a look at the delays between the LSB and successive bits.


I spent the afternoon re-working my ugly SOIC adapter board designs to reduce the ground-connection impedance and add on-board bypass caps. Sign up Already a member? About Us Contact Hackaday. The 74VHC is another candidate – it has twin 4-bit counters dtaasheet a package, so three ICs would be necessary.

Yes, delete darasheet Cancel. Don’t forget that ground-bounce! Since it’s a ripple counter, Q0 flips, then Q1, then Q2, etc, so we have to add all the delays so see how long it takes for the address to settle to the next value. I haven’t used VHC logic before, but keep seeing it around.

74HC Datasheet PDF –

This also ignores the fact that two 74HCs need to be chained to generate the bit address: In this case, it’s not memory but registers.

The row address can be updated from the horizontal sync. If I were going to build a bunch of these, I’d try harder to get the 74HC to work.

Synchronization is an issue, but it’s worth thinking about – maybe if the PIC runs from datashet external This would work – with the 12ns SRAM access time, still way under the 40ns cycle time.

If I were making more than a one-off project, I think the 25 MHz idea might be the way to go. Did I miss something on the ripple counters? Monitors can handle some clock frequency variations. The dot clock is Cycling back the hsync for a second counter is interesting.

Synchronous counters use extra logic to form the next state from the previous one directly, without waiting for clocks to ripple through, so the outputs settle faster.

In the store-each-dot-period-as-a-byte plan, this is trivial – I have full and easy control of all the singals on on a per-dot basis. The clock input on the ‘ works on the positive edge, so the schematic above changes a bit, but at least the addresses seem OK.


74HC datasheet(1/24 Pages) PHILIPS | stage binary ripple counter

I started with the VHC part this time: Next step – the rest of the logic and timing calculations. Here’s a simplified schematic of the guts of the VGA framebuffer it ignores the reset and connections between the two ”s required to generate 19 bits of address. I think either one would definitely work, and it would make an interesting project, but I’ve somehow got it into my head that I need actual x I’ll have to give that one some thought.

Maybe a fast external counter for the lowest 4 or 8 bits, and the PIC generates the upper ones? I need 5 of them, which sucks. Synchronous Counters Synchronous counters use extra logic to form the next state from the previous one directly, without waiting for clocks to ripple through, so the outputs settle faster.


How about the 74HC? Maybe I’m doing this wrong? That should relax some timing as your MSB are no longer rely on the propagation from the lower bits. Musta been a bunch of pixie-dust in there, or a poor memory of 18 years ago. So, with two of them connected to generate 19 bits of address, the tpd from the clock edge to the MSB settling is: